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| SN74LS161A SN74LS163A BCD Decade Counters/ 4-Bit Binary Counters The LS161A / 163A are high-speed 4-bit synchronous counters. They are edge-triggered, synchronously presettable, and cascadable MSI building blocks for counting, memory addressing, frequency division and other applications. The LS161A and LS163A count modulo 16 (binary). The LS161A has an asynchronous Master Reset (Clear) input that overrides, and is independent of, the clock and all other control inputs. The LS163A has a Synchronous Reset (Clear) input that overrides all other control inputs, but is active only during the rising clock edge. Binary (Modulo 16) Asynchronous Reset Synchronous Reset LS161A LS163A http://onsemi.com LOW POWER SCHOTTKY * * * * * * Synchronous Counting and Loading Two Count Enable Inputs for High Speed Synchronous Expansion Terminal Count Fully Decoded Edge-Triggered Operation Typical Count Rate of 35 MHz ESD > 3500 Volts 16 1 PLASTIC N SUFFIX CASE 648 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current - High Output Current - Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 - 0.4 8.0 Unit V C mA mA 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS161AN SN74LS161AD SN74LS163AN SN74LS163AD Package 16 Pin DIP 16 Pin 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel 2000 Units/Box 2500/Tape & Reel (c) Semiconductor Components Industries, LLC, 1999 1 December, 1999 - Rev. 0 Publication Order Number: SN74LS161A/D SN74LS161A SN74LS163A CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. *MR for LS161A *SR for LS163A 1 *R 2 CP 3 P0 4 P1 5 P2 6 P3 8 7 CEP GND LOADING (Note a) PIN NAMES PE P0 - P3 CEP CET CP MR SR Q0 - Q3 TC Parallel Enable (Active LOW) Input Parallel Inputs Count Enable Parallel Input Count Enable Trickle Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Synchronous Reset (Active LOW) Input Parallel Outputs Terminal Count Output HIGH 1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 10 U.L. 10 U.L. LOW 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 5 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. LOGIC SYMBOL 9 3 4 5 6 7 10 2 PE P0 P1 P2 P3 CEP CET CP TC 15 *R Q0 Q1 Q2 Q3 1 14 13 12 11 VCC = PIN 16 GND = PIN 8 *MR for LS161A *SR for LS163A http://onsemi.com 2 SN74LS161A SN74LS163A STATE DIAGRAM LS161A * LS163A 0 1 2 3 LOGIC EQUATIONS 4 Count Enable = CEP * CET * PE TC for LS161A & LS163A = CET * Q0 * Q1 * Q2 * Q3 Preset = PE * CP + (rising clock edge) Reset = MR (LS161A) Reset = SR * CP + (rising clock edge) Reset = (LS163A) 15 5 14 6 13 7 12 11 10 9 8 FUNCTIONAL DESCRIPTION The LS161A / 163A are 4-bit synchronous counters with a synchronous Parallel Enable (Load) feature. The counters consist of four edge-triggered D flip-flops with the appropriate data routing networks feeding the D inputs. All changes of the Q outputs (except due to the asynchronous Master Reset in the LS161A) occur as a result of, and synchronous with, the LOW to HIGH transition of the Clock input (CP). As long as the set-up time requirements are met, there are no special timing or activity constraints on any of the mode control or data inputs. Three control inputs -- Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) -- select the mode of operation as shown in the tables below. The Count Mode is enabled when the CEP, CET, and PE inputs are HIGH. When the PE is LOW, the counters will synchronously load the data from the parallel inputs into the flip-flops on the LOW to HIGH transition of the clock. Either the CEP or CET can be used to inhibit the count sequence. With the PE held HIGH, a LOW on either the CEP or CET inputs at least one set-up time prior to the LOW to HIGH clock transition will cause the existing output states to be retained. The AND feature of the two Count Enable inputs (CET * CEP) allows synchronous cascading without external gating and without delay accumulation over any practical number of bits or digits. The Terminal Count (TC) output is HIGH when the Count Enable Trickle (CET) input is HIGH while the counter is in its maximum count state (HLLH for the BCD counters, HHHH for the Binary counters). Note that TC is fully decoded and will, therefore, be HIGH only for one count state. The LS161A and LS163A count modulo 16 following a binary sequence. They generate a TC when the CET input is HIGH while the counter is in state 15 (HHHH). From this state they increment to state 0 (LLLL). The Master Reset (MR) of the LS161A is asynchronous. When the MR is LOW, it overrides all other input conditions and sets the outputs LOW. The MR pin should never be left open. If not used, the MR pin should be tied through a resistor to VCC, or to a gate output which is permanently set to a HIGH logic level. The active LOW Synchronous Reset (SR) input of the LS163A acts as an edge-triggered control input, overriding CET, CEP and PE, and resetting the four counter flip-flops on the LOW to HIGH transition of the clock. This simplifies the design from race-free logic controlled reset circuits, e.g., to reset the counter synchronously after reaching a predetermined value. MODE SELECT TABLE *SR L H H H H PE X L H H H CET X X H L X CEP X X H X L Action on the Rising Clock Edge ( RESET (Clear) LOAD (Pn Qn ) COUNT (Increment) NO CHANGE (Hold) NO CHANGE (Hold) ) *For the LS163A only. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care http://onsemi.com 3 SN74LS161A SN74LS163A LS161A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 - 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 Input HIGH Current MR, Data, CEP, Clock PE, CET MR, Data, CEP, Clock PE, CET IIL IOS ICC Input LOW Current MR, Data, CEP, Clock PE, CET Short Circuit Current (Note 1) Power Supply Current Total, Output HIGH Total, Output LOW - 20 0.5 20 40 0.1 0.2 - 0.4 - 0.8 - 100 31 32 V A mA IOL = 8.0 mA 0.4 Min 2.0 0.8 - 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V IIH mA mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. LS163A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 - 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 Input HIGH Current Data, CEP, Clock PE, CET, SR Data, CEP, Clock PE, CET, SR IIL IOS ICC Input LOW Current Data, CEP, Clock, PE, SR CET Short Circuit Current (Note 1) Power Supply Current Total, Output HIGH Total, Output LOW - 20 0.5 20 40 0.1 0.2 - 0.4 - 0.8 - 100 31 32 V A mA IOL = 8.0 mA 0.4 Min 2.0 0.8 - 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V IIH mA mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. http://onsemi.com 4 SN74LS161A SN74LS163A AC CHARACTERISTICS (TA = 25C) Limits Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Clock to TC Propagation Delay Clock to Q Propagation Delay CET to TC MR or SR to Q Min 25 Typ 32 20 18 13 18 9.0 9.0 20 35 35 24 27 14 14 28 Max Unit MHz ns ns ns ns VCC = 5.0 V CL = 15 pF Test Conditions AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol tWCP tW ts ts th th trec Parameter Clock Pulse Width Low MR or SR Pulse Width Setup Time, other* Setup Time PE or SR Hold Time, data Hold Time, other Recovery Time MR to CP Min 25 20 20 25 3 0 15 Typ Max Unit ns ns ns ns ns ns ns VCC = 5.0 V Test Conditions *CEP, CET, or DATA DEFINITION OF TERMS SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) -- is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) -- is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. AC WAVEFORMS tW(H) CP 1.3 V tPHL Q 1.3 V tW(L) 1.3 V tPLH 1.3 V OTHER CONDITIONS: PE = MR (SR) = H CEP = CET = H MR 1.3 V tW trec 1.3 V OTHER CONDITIONS: PE = L P0 = P1 = P2 = P3 = H CP Q0 Q1 Q2 Q3 tPHL 1.3 V Figure 1. Clock to Output Delays, Count Frequency, and Clock Pulse Width Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time http://onsemi.com 5 SN74LS161A SN74LS163A AC WAVEFORMS (continued) COUNT ENABLE TRICKLE INPUT TO TERMINAL COUNT OUTPUT DELAYS The positive TC pulse occurs when the outputs are in the (Q0 * Q1 * Q2 * Q3) state for the LS161 and LS163. TC CET 1.3 V tPLH 1.3 V 1.3 V tPHL 1.3 V Figure 3. OTHER CONDITIONS: CP = PE = CEP = MR = H CLOCK TO TERMINAL COUNT DELAYS CP The positive TC pulse is coincident with the output state (Q0 * Q1 * Q2 * Q3) for the LS161 and LS163. TC 1.3 V tPLH 1.3 V 1.3 V 1.3 V tPHL 1.3 V Figure 4. OTHER CONDITIONS: PE = CEP = CET = MR = H CP 1.3 V th(H) = 0 1.3 V ts(L) 1.3 V 1.3 V th(L) = 0 1.3 V SETUP TIME (ts) AND HOLD TIME (th) FOR PARALLEL DATA INPUTS The shaded areas indicate when the input is permitted to change for predictable output performance. P0 * P1 * P2 * P3 ts(H) Q0 * Q1 * Q2 * Q3 Figure 5. OTHER CONDITIONS: PE = L, MR = H SETUP TIME (ts) AND HOLD TIME (th) FOR COUNT ENABLE (CEP) AND (CET) AND PARALLEL ENABLE (PE) INPUTS The shaded areas indicate when the input is permitted to change for predictable output performance. 1.3 V th (L) = 0 1.3 V PARALLEL LOAD (See Fig. 5) Q RESPONSE TO PE RESET Q RESPONSE TO SR COUNT OR LOAD Q OTHER CONDITIONS: PE = H, MR = H ts(H) 1.3 V CP th(H) = 0 1.3 V COUNT MODE (See Fig. 7) CEP ts(H) CET 1.3 V ts(H) CP ts(L) SR or PE 1.3 V th(H) = 0 1.3 V th(H) = 0 1.3 V COUNT ts(L) 1.3 V th(L) = 0 1.3 V ts(L) 1.3 V HOLD 1.3 V th(L) = 0 1.3 V HOLD Figure 6. Figure 7. http://onsemi.com 6 SN74LS161A SN74LS163A PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 9 -B- 1 8 P 8 PL 0.25 (0.010) M B S G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S DIM A B C D F G J K M P R http://onsemi.com 7 SN74LS161A SN74LS163A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION North America Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 2:30pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 2:30pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 1:30pm to 5:00pm UK Time) Email: ONlit@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong 800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5487-8345 Email: r14153@onsemi.com Fax Response Line: 303-675-2167 800-344-3810 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 SN74LS161A/D |
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